1. Field of the Invention
The present invention is directed generally to a semiconductor memory device, and, more particularly, to a semiconductor memory burst length count determination detector circuit.
2. Description of the Background
In a conventional memory device, an address and a read or write command are presented to the device. A clock internal to the device controls the time at which the read or write command is performed. An address must be presented for each memory location at which a read or write is desired. The speed of completion of the read or write is thus limited by the speed of the internal clock. The internal clock must also operate compatibly with the speed of the microprocessor. Memory device read and write operations are often performed on sequentially addressable locations, or blocks of data, of the device. Each sequential address must be presented to the memory device at a cost of system speed and resources.
Synchronous semiconductor memory devices have been developed to eliminate the problems inherent in internally clocked memory devices. Typical synchronous memory devices operate in a burst mode. In burst mode, an external address and a read or write command are presented to the memory device and the address is latched into a burst counter. The burst counter is connected to a burst address decoder which decodes the first address and presents it to the array of memory cells within the device to complete the read or write operation. The burst counter then increments or decrements the address in response to a clock that is synchronous with the processing speed of the microprocessor. The address is incremented or decremented depending on the burst length of the memory device. Thus, the addresses of sequential locations in the device are generated internally, making read or write operations to sequential memory locations more efficient.
Typical synchronous memory devices have burst counters that are capable of operation in either a linear burst mode, an interleaved burst mode, or both a sequential burst mode and an interleaved burst mode. Burst counters that operate in the linear burst mode increment the external address and each subsequent internally generated address by 1 upon each tick of the synchronous clock. Burst counters that operate in the interleaved burst mode invert the least significant bit of the external address to form the first internal address. Subsequently, the counter alternately inverts the two least significant bits of the prior internal address and the least significant bits of the prior internal address. The interleaved burst mode is a more efficient method of generating burst addresses in cache memory devices, which typically have data arranged in blocks of data, or pages, that are copied from a main memory device. The interleaved burst mode of operation ensures that the remainder of a page of data will be loaded into the cache device if the initial load address is in the middle of a page.
It is desirable for a synchronous memory device that operates in burst mode to have a burst length count determination detector in communication with the burst length counter. A typical burst length count determination detector receives the outputs of the burst counter and receives control signals that can be used to select the burst length. The burst length count determination detector compares the burst length counter outputs with the burst length inputs to determine when the burst operation has completed. The burst length count determination detector outputs a signal that signals the end of the burst operation. The signal is useful to turn the column address decoder and the input and output buffers off at the completion of the burst operation, thus resulting in a power savings. Also, certain circuits are reset and available for subsequent operations, or the signal may trigger subsequent operations.